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2018-12-13nir: Add a saturated unsigned integer add opcodeIan Romanick1-0/+2
2018-12-13nir/lower_int64: Add support for [iu]mul_highJason Ekstrand2-0/+67
2018-12-13nir: Allow [iu]mul_high on non-32-bit typesJason Ekstrand2-4/+40
2018-12-13glx: mandate xf86vidmode only for "drm" dri platformsEmil Velikov1-2/+4
2018-12-13nir: remove unused variableAlejandro Piñeiro1-1/+0
2018-12-13virgl: work around bad assumptions in virglrendererErik Faye-Lund1-1/+32
2018-12-13virgl: wrap vertex element state in a structErik Faye-Lund2-9/+21
2018-12-13virgl: simplify virgl_hw_set_index_bufferErik Faye-Lund1-3/+2
2018-12-13virgl: simplify virgl_hw_set_vertex_buffersErik Faye-Lund1-4/+2
2018-12-13radv: don't check if format is depth in radv_image_can_enable_hile()Samuel Pitoiset1-1/+0
2018-12-13radv: check if addrlib enabled HTILE in radv_image_can_enable_htile()Samuel Pitoiset1-1/+2
2018-12-13radv: switch on EOP when primitive restart is enabled with triangle stripsSamuel Pitoiset1-2/+1
2018-12-13radv: allow to skip DCC decompressions with the new predicateSamuel Pitoiset1-6/+13
2018-12-13radv: add a predicate for reflecting DCC decompression stateSamuel Pitoiset5-1/+44
2018-12-12i965/compute: Emit GPGPU_WALKER in genX_state_uploadJordan Justen3-130/+105
2018-12-12i965/genX_state: Add register access functionsJordan Justen1-0/+31
2018-12-12intel: Simplify the half-float packing in image load/store lowering.Eric Anholt1-8/+2
2018-12-12nir: Pull some of intel's image load/store format conversion to nir_format.hEric Anholt2-18/+40
2018-12-12nir: Add some more consts to the nir_format_convert.h helpers.Eric Anholt1-7/+6
2018-12-13nir: detect more induction variablesTimothy Arceri1-0/+36
2018-12-13nir: reword code commentTimothy Arceri1-2/+2
2018-12-13nir: in loop analysis track actual control flow typeTimothy Arceri1-13/+21
2018-12-13nir: add if opt opt_if_loop_last_continue()Danylo Piliaiev1-0/+95
2018-12-13nir: rework force_unroll_array_access()Timothy Arceri1-14/+35
2018-12-13nir: factor out some of the complex loop unroll code to a helperTimothy Arceri1-51/+64
2018-12-12meson: libfreedreno depends upon libdrm (for fence support)Rhys Kidd1-3/+1
2018-12-12nir: Document the function inlining processJason Ekstrand1-0/+68
2018-12-12intel/blorp: Assert that we don't re-layout a compressed surfaceJason Ekstrand1-0/+3
2018-12-12anv/pipeline: Set the correct binding count for compute shadersJason Ekstrand1-2/+6
2018-12-12radv: bump reported version to 1.1.90Samuel Pitoiset1-1/+1
2018-12-12virgl: force linear texturing supportErik Faye-Lund1-2/+3
2018-12-12intel/compiler: do not copy-propagate strided regions to ddx/ddy argumentsIago Toral Quiroga1-0/+21
2018-12-11anv: Advertise support for MinLod on Skylake+Jason Ekstrand2-1/+2
2018-12-11intel/fs: Support min_lod parameters on texture instructionsJason Ekstrand4-2/+31
2018-12-11nir/lower_tex: Add lowering for some min_lod casesJason Ekstrand2-0/+116
2018-12-11nir/lower_tex: Modify txd instructions instead of replacing themJason Ekstrand1-41/+7
2018-12-11nir/lower_tex: Simplify lower_gradient logicJason Ekstrand1-12/+9
2018-12-11spirv: Add support for MinLodJason Ekstrand4-1/+16
2018-12-11intel/ir: Don't allow allocating zero registersJason Ekstrand1-0/+1
2018-12-12gallivm: remove unused float coord wrapping for aos samplingRoland Scheidegger1-507/+23
2018-12-11freedreno: Add .dir-locals to the common directoryNeil Roberts1-0/+8
2018-12-11mesa/st/nir: fix missing nir_compact_varyingsRob Clark1-1/+2
2018-12-11nir: fix spelling typoRob Clark1-1/+1
2018-12-11anv,radv: Disable VK_EXT_pci_bus_infoJason Ekstrand2-2/+2
2018-12-10glapi: fixup EXT_multisampled_render_to_texture dispatchKristian H. Kristensen5-5/+17
2018-12-10freedreno: Fix the Makefile.am fixKristian H. Kristensen1-3/+0
2018-12-10i965/fs: Handle V/UV immediates in dump_instructions()Matt Turner1-0/+5
2018-12-10intel/compiler: Always print flag subregister numberSagar Ghuge1-7/+6
2018-12-10intel/compiler: Set swizzle to BRW_SWIZZLE_XXXX for scalar regionSagar Ghuge1-1/+18
2018-12-10meson: Add nir_algebraic_parser_test to suitesDylan Baker1-0/+1
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